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Author Tavakolinia, Atefeh, author.
Title FPGA power optimization / by Atefeh Tavakolinia.
Published [Northridge, California] : California State University, Northridge, 2013.
LOCATION CALL # STATUS
 Electronic Book  TA153 .Z953 2013 T38eb    ONLINE
  
Description 1 online resource (vii, 42 pages) : illustrations, color.
Content Type text
still image
Format online resource
File Characteristics text file PDF
Thesis M.S. California State University, Northridge 2013.
Bibliography Includes bibliographical references (page 42).
Note Description based on online resource; title from PDF title page (viewed on Aug. 8, 2013).
Summary The project shows a rundown of Xilinx series 7 FPGA low-power design techniques at various stages of the development cycle. In a given FPGA design, power has become a primary factor. Therefore power management would be critical in most applications. Specifying maximum power per chip or system is becoming the industry standard. As such, designers have to bring power much earlier in the design flow. By lowering power, longer life for battery and higher reliability for the system is achieved. Transistors are becoming smaller in each generation of chip technology. This phenomenon has lead to more leakage within each transistor. More leakage leads to more static power - which is the current of the transistors when they are turned off. By increasing FPGA performance (i.e. higher clock rate), the FPGA dynamic power has also increased. This project covers different techniques for SRAM based FPGA power optimization with design examples verifying the validity of the power optimization.
Subject Field programmable gate arrays -- Design.
Local Subject Dissertations, Academic -- CSUN -- Engineering -- Electrical and Computer Engineering.
Alternate Title Field programmable gate array power optimization
OCLC number 855551289