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Author Srinidhi, Raghunandan, author.
Title MIPS processor implementation / by Raghunandan Srinidhi.
Published [Northridge, California] : California State University, Northridge, 2012.
LOCATION CALL # STATUS
 Electronic Book  TA153 .Z953 2012 S65eb    ONLINE
  
Description 1 online resource (viii, 84 pages) + 2 text files, 1 compressed data file.
Content Type text
Format online resource
File Characteristics text file PDF
data file RAR
Note Accompanying files contain multi cycle CPU output data, VHDL codes of multicycle CPU, and source files.
Thesis M.S. California State University, Northridge 2012.
Bibliography Includes bibliographical references (page 34).
Summary The scope of the project was to implement the design of a Multi Cycle Central Processing Unit (CPU) in Very-High-Speed Integrated Circuits (VHSIC) Hardware Description Language or commonly known as VHDL. The implementation was carried out to understand the development of processor hardware as the design and customization of embedded processors has become a mainstream task in the development of complex SoCs (Systems-on-Chip).
Note Description based on online resource; title from PDF title page (viewed on June 05, 2012).
Subject Microprocessors -- Design.
Very high speed integrated circuits.
VHDL (Computer hardware description language)
Local Subject Dissertations, Academic -- CSUN -- Engineering -- Electrical and Computer Engineering.
OCLC number 849349608