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Author Sadeghi, Sahar, author.
Title Design and development of memory mapping for an image data acquisition system / by Sahar Sadeghi.
Published [Northridge, California] : California State University, Northridge, 2012.
LOCATION CALL # STATUS
 Electronic Book  TA153 .Z953 2012 S23eb    ONLINE
  
Description 1 online resource (viii, 75 pages) : illustrations, some color.
Content Type text
still image
Format online resource
File Characteristics text file PDF
Thesis M.S. California State University, Northridge 2012.
Bibliography Includes bibliographical references (page 64).
Summary In this thesis project, a memory mapping process for an image data acquisition system, which is built out of three levels of arrays of FPGA, has been developed. The system has the capability to sample the outputs of large number of photo-detectors with high resolution and at a very high frequency. The received data is sampled, digitalized and passed through a three levels of FPGAs to a fiber channel switch which provides the final high speed serial output. The array has 256₉256 of photo detectors. Each 16 detectors of the array are grouped to make a 4₉4 photo detector array module. A sample from all detectors will represent one frame. To form one image, 16 frames are required. Therefore, all the detectors of the array are sampled simultaneously sixteen times to form the 16 frames. The analog signal sample out of each detector is converted into 12-bit digital value. BRAM (16₉49154) is used to store the collected data in each level and define the address of each detector. The time required to sample, digitize and process the collected data through the three levels of FPGA is 0.774ms.
Note Description based on online resource; title from PDF title page (viewed on June 01, 2012).
Subject Memory maps (Computer science) -- Design.
Image processing.
Analog-to-digital converters.
Local Subject Dissertations, Academic -- CSUN -- Engineering -- Electrical and Computer Engineering.
OCLC number 847714667