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Author Raval, Tejas, author.
Title Asynchronous interface ASIC flow (RTL-to-GDSII) using Cadence and Synopsys tools / by Tejas Raval.
Published [Northridge, California] : California State University, Northridge, 2012.
LOCATION CALL # STATUS
 Electronic Book  TA153 .Z953 2012 R38eb    ONLINE
  
Description 1 online resource (vii, 143 pages) : illustrations, some color.
Content Type text
still image
Format online resource
File Characteristics text file PDF
Thesis M.S. California State University, Northridge 2012.
Bibliography Includes bibliographical references (page 106).
Summary The aim of this project is to successfully complete ASIC design flow from RTL to GDSII using advanced industry-level tools. This project provides a solid base and practical hands-on experience of advanced tools like Cadence NC Simulator (Behavioral Simulation and Post Synthesis Simulation), Synopsys Design Compiler (Logic Synthesis), Synopsys DFT Compiler (Logic Scan Insertion and Boundary Scan Insertion), Synopsys Power Compiler (Power Optimization using clock gating), Synopsys Tetra Max (Determine Fault Coverage) and Synopsys IC Compiler (Design planning, Power Network Synthesis, Clock Tree Synthesis, Place and Route and Chip Finishing). The analysis of various design factors affecting the performance of the final chip such as power, area and timing is also performed.
Note Description based on online resource; title from PDF title page (viewed on June 04, 2012).
Subject Application-specific integrated circuits -- Design.
Asynchronous circuits -- Design.
Local Subject Dissertations, Academic -- CSUN -- Engineering -- Electrical and Computer Engineering.
Alternate Title Implementation of asynchronous interface ASIC flow (RTL-to-GDSII) using Cadence and Synopsys tools
OCLC number 847538407