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Author Mehta, Shashank, author.
Title Design synthesizable USB 3.0 using Verilog HDL and simulate design using Cadence / by Shashank Mehta.
Published [Northridge, California] : California State University, Northridge, 2012.
LOCATION CALL # STATUS
 Electronic Book  TA153 .Z953 2012 M44eb    ONLINE
  
Description 1 online resource (x, 82 pages) : illustrations, some color.
Content Type text
still image
Format online resource
File Characteristics text file PDF
Thesis M.S. California State University, Northridge 2012.
Bibliography Includes bibliographical references (page 48).
Summary In this project the author designs USB 3.0 using Verilog HDL and simulates the design in Cadence. The design includes two layers of USB 3.0: Physical Layer and Link Layer. Along with USB 2.0 functionality, it includes Superspeed functionality. The Physical Layer contains PCI Express and PIPE interface. The design transfers data from transmitter to receiver serially. Data is transferred either on 2.5GT/s or on 5.0GT/s, depending upon the mode and rate. The design generates a clock that runs on two different frequencies (i.e. 125MHz and 250MHz) that are used to transfer data on parallel interfaces. Data are captured that are coming asynchronously and lock the receiver clock with incoming asynchronous serial data. The Link Layer contains Link Transition and Status State Machine (LTSSM). This is used to manage the link between two ports. It manages the Superspeed and power of the link by putting the link into the appropriate stage according to its usage.
Note Description based on online resource; title from PDF title page (viewed on May 30, 2012).
Subject USB (Computer bus) -- Design.
Verilog (Computer hardware description language)
Local Subject Dissertations, Academic -- CSUN -- Engineering -- Electrical and Computer Engineering.
OCLC number 847540781