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Author Kamarajugadda, Kartik.
Title Synthesis and simulation of multicycle processor design in VHDL using synopsys design compiler / by Kartik Kamarajugadda.
Published 2011.
LOCATION CALL # STATUS
 Floor3  TA153 .Z953 2011 K36    IN LIBRARY
 Stored Special Collections & Archives  TA153 .Z953 2011 K36    IN LIBRARY
  
Description ix, 77 leaves : ill. ; 28 cm.
Thesis Thesis (M.S.)--California State University, Northridge, 2011.
Bibliography Includes bibliographical references (leaf 35).
Local Subject Dissertations, Academic -- CSUN -- Engineering -- Electrical and Computer Engineering.
Spine Title Multicycle processor in VHDL using synopsys DC
OCLC number 809724016