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Author Ramos, Alitea Laya.
Title Bram and DSP design configuration for burn-in test of virtex-4 FPGA / by Alitea Laya Ramos.
Published 2011.
LOCATION CALL # STATUS
 Floor3  TA153 .Z953 2011 R36    IN LIBRARY
 Stored Special Collections & Archives  TA153 .Z953 2011 R36    IN LIBRARY
  
Description viii, 49 leaves : ill. (some col.) ; 28 cm.+ 1 CD-ROM (4 3/4 in.).
Thesis Thesis (M.S.)--California State University, Northridge, 2011.
Bibliography Includes bibliographical references (leaf 49).
Local Subject Dissertations, Academic -- CSUN -- Engineering -- Electrical and Computer Engineering.
Spine Title Bram & DSP design confi 4 burn-in TST of virtex-4 FPGA
Other Title Bram and digital signal processing design configuration for burn-in test of virtex-4 field programmable gate array
OCLC number 809568693